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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 13d. V GATE _ Calculation Trigger Condition
SOFTWARE CONFIGURATION
SETTINGS
V GATE_ CALCULATION TRIGGER CONDITIONS
TCOMP_ = 1
APCCOMP_ = 1
APCSRC_1 = 0
APCSRC_0 = 0
?
?
?
Temperature measurements vary enough to exceed the hysteresis settings
A write command to the APC_ Parameter register
A write command to the VSET register through the serial interface
TCOMP_ = 1
APCCOMP_ = 1
APCSRC_1 = 1
APCSRC_0 = X
TCOMP_ = 1
APCCOMP_ = 0
APCSRC_1 = X
APCSRC_0 = X
TCOMP = 0
APCCOMP = 1
APCSRC_1 = 0
APCSRC_0 = 0
TCOMP = 0
APCCOMP = 1
APCSRC_1 = 1
APCSRC_0 = X
TCOMP = 0
APCCOMP = 0
APCSRC_1 = X
APCSRC_0 = X
X = Don’t care.
? Temperature measurements vary enough to exceed the hysteresis settings
? Current-sense measurements or ADCIN_ samples vary enough to cause a new LUT
value to be retrieved (depends on PSIZE and INT values in the LUT Configuration
registers)
? A write command to the VSET register through the serial interface
? Temperature measurements vary enough to exceed the hysteresis settings
? A write command to the VSET register through the serial interface
? A write command to the APC_ register through the serial interface
? A write command to the VSET register through the serial interface
? Current-sense measurements vary enough to exceed the hysteresis settings
? A write command to the VSET register through the serial interface
? A write command to the VSET register through the serial interface
Set SELFTIME to 1 and DOCAL to 1 to perform calibra-
tions of PGA1 and PGA2 on a self-timed periodic basis
(approximately every 13ms). When SELFTIME is set to
0, writing to PGACAL with DOCAL set to 1 manually
triggers PGA calibration.
ADC Conversion Register (ADCCON) (Write Only)
Write to the ADC Conversion register to select which
channels are converted and to set the ADC for continu-
ous conversion of each selected channel (see Table
20). Set CONCONV to 1 to configure the ADC to per-
form continuous conversions of the selected channels.
Bits D[6:0] select which channels are converted. Select
which channel is to be converted by setting the corre-
sponding bit to 1. Any channel that is set to 0 will not
be converted. Depending on the ADC clock mode that
is selected in the Hardware Configuration register (see
the Internally Timed Acquisitions and Conversions sec-
tion and Table 11), writing to the ADC Conversion reg-
ister initiates an ADC conversion of the selected
channel or the next selected channel in the sequence if
more than one channel is selected (see the ADC
Conversion Scheduling section). Bits D[15:8] are don’t-
care bits.
______________________________________________________________________________________
55
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